Divider-less phase locked loop (PLL) architecture is one of the techniques used for fractional frequency generation. However, the lack of a divider in the PLL feedback loop reduces the phase detector range to only one cycle of the PLL output frequency. Additionally, divider-less PLL architecture have higher sensitivity to reference jitter. For example, an increase in the reference jitter can results in a false measurement from the PLL's time-to-digital converter (TDC), which can cause the PLL to lose lock and shift its output frequency with regard to the target output frequency.